LAN8742AI-CZ datasheet(111/124 Pages) MICROCHIP

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 2013-2015 Microchip Technology Inc.

DS00001989A-page 111

LAN8742A/LAN8742Ai

5.6.4.2

RMII Timing (REF_CLK In Mode)

The 50 MHz REF_CLK IN timing applies to the case when nINTSEL is floated or pulled-high. In this mode, a 50 MHz

clock must be input on the CLKIN pin. For more information on REF_CLK In Mode, see Section 3.7.4, "nINTSEL:

nINT/REFCLKO Configuration".

Note 1: Timing was designed for system load between 10 pF and 25 pF.

Note:

The CRS_DV pin performs both carrier sense and data valid functions. CRS_DV is asserted asynchro-

nously on detection of carrier due to the criteria relevant to the operating mode. If the PHY has additional

bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, then the device will assert

CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble and deassert CRS_DV on

cycles of REF_CLK which present the first di-bit of a nibble. For additional information, refer to the RMII

specification.

FIGURE 5-5:

RMII TIMING (REF_CLK IN MODE)

TABLE 5-13:

RMII TIMING VALUES (REF_CLK IN MODE)

Symbol

Description

Min.

Typ.

Max.

Unit

Note

tclkp

CLKIN period

tclkh

CLKIN high time

tclkp * 0.35

tclkp * 0.65

tclkl

CLKIN low time

tclkp * 0.35

tclkp * 0.65

toval

RXD[1:0], RXER, CRS_DV output

valid from rising edge of CLKIN

15.0

(see Note 1)

toinvld

RXD[1:0], RXER, CRS_DV output

invalid from rising edge of CLKIN

3.0

(see Note 1)

tsu

TXD[1:0], TXEN setup time to ris-

ing edge of CLKIN

4.0

(see Note 1)

tihold

TXD[1:0], TXEN input hold time

after rising edge of CLKIN

1.5

(see Note 1)

tclkh

tclkl

tclkp

toval

toinvld

toval

toinvld

tsu tihold

tihold

tsu

tihold

CLKIN

(REF_CLK)

(INPUT)

RXD[1:0], RXER

(OUTPUTS)

CRS_DV

(OUTPUT)

TXD[1:0]

(INPUTS)

TXEN

(INPUT)

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