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MB91F577CSPMC 데이터시트(PDF) 148 Page - Cypress Semiconductor

부품명 MB91F577CSPMC
상세설명  32-bit RISC, load/store architecture, 5-stage pipeline
PDF  163 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB91F577CSPMC 데이터시트(HTML) 148 Page - Cypress Semiconductor

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Document Number: 002-04725 Rev.*A
Page 148 of 163
MB91570 Series
13.4.16 External bus I/F (ready) timing
(TA: Recommended operating conditions, VCC5 = VCCE = AVCC = 5.0V±10%, VSS = AVSS = 0.0V)
(External load capacitance 50pF)
Parameter
Symbol
Pin name
Value
Unit
Remarks
Min
Max
Cycle time
tCYC
SYSCLK
50
–
ns
If using RDY, set SYSCLK to
20 MHz or less.
RDY setup time→
SYSCLK ↑
tRDYS
SYSCLK,
RDY
28
–
ns
SYSCLK ↑→
RDY hold time
tRDYH
SYSCLK,
RDY
0
–
ns
External bus I/F (ready) timing
Added cycle by RDY
t4
t3
t5
SYSCLK
ASX
CS0X to CS3X
RDX
RDY
tRDYS
tRDYH
t6
RWT=2
CSRD=2
ASCY=2
ACS=2
RDCS=2
t1
t2
tCYC
Auto wait cycle



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