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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT89C51CC03U-RDTIM 데이터시트(PDF) 115 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM 데이터시트(HTML) 115 Page - ATMEL Corporation |
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115 / 195 page  115 AT89C51CC03 4182I–CAN–06/05 Table 60. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers 1 Note: The CAN controller bit timing registers must be accessed only if the CAN controller is dis- abled with the ENA bit of the CANGCON register set to 0. See Figure 52. No default value after reset. 76 543 210 - BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6-1 BRP5:0 Baud rate prescaler The period of the CAN controller system clock Tscl is programmable and determines the individual bit timing. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. Tscl = BRP[5..0] + 1 Fcan |
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