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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT89C51CC03U-RDTIM 데이터시트(PDF) 157 Page - ATMEL Corporation |
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AT89C51CC03U-RDTIM 데이터시트(HTML) 157 Page - ATMEL Corporation |
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157 / 195 page  157 AT89C51CC03 4182I–CAN–06/05 Registers Table 103. ADCF Register ADCF (S:F6h) ADC Configuration Reset Value =0000 0000b Table 104. ADCON Register ADCON (S:F3h) ADC Control Register Reset Value =X000 0000b 76 543 210 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number Bit Mnemonic Description 7-0 CH 0:7 Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. 76 543 210 - PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0 Bit Number Bit Mnemonic Description 7- 6 PSIDLE Pseudo Idle Mode (Best Precision) Set to put in idle mode during conversion Clear to convert without idle mode. 5ADEN Enable/Standby Mode Set to enable ADC Clear for Standby mode (power dissipation 1 uW). 4ADEOC End Of Conversion Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software. 3 ADSST Start and Status Set to start an A/D conversion. Cleared by hardware after completion of the conversion 2-0 SCH2:0 Selection of Channel to Convert see Table 102 |
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