STM32F411CC datasheet(104/149 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F411xC STM32F411xE

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DocID026289 Rev 6

6.3.18

TIM timer characteristics

The parameters given in Table 57 are guaranteed by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

6.3.19

Communications interfaces

I2C interface characteristics

The I2C interface meets the requirements of the standard I2C communication protocol with

the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-

drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is

disabled, but is still present.

The I2C characteristics are described in Table 58. Refer also to Section 6.3.16: I/O port

characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400

kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the

complete solution, please contact your local ST sales representative.

Table 57. TIMx characteristics(1)(2)

1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.

2. Guaranteed by design.

Symbol

Parameter

Conditions(3)

3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE

bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise

TIMxCLK >= 4x PCLKx.

Min

Max

Unit

tres(TIM)

Timer resolution time

AHB/APBx prescaler=1

or 2 or 4, fTIMxCLK =

100 MHz

tTIMxCLK

11.9

AHB/APBx prescaler>4,

fTIMxCLK = 100 MHz

tTIMxCLK

11.9

fEXT

Timer external clock

frequency on CH1 to CH4 f

TIMxCLK = 100 MHz

fTIMxCLK/2

MHz

050

MHz

ResTIM

Timer resolution

16/32

bit

tCOUNTER

16-bit counter clock

period when internal clock

is selected

fTIMxCLK = 100 MHz

0.0119

780

µs

tMAX_COUNT

Maximum possible count

with 32-bit counter

65536 ×

65536

tTIMxCLK

fTIMxCLK = 100 MHz

-51.1

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