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OMAP3530ECUS72 데이터시트(PDF) 242 Page - Texas Instruments

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부품명 OMAP3530ECUS72
상세설명  Applications Processors
PDF  265 Pages
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제조업체  TI1 [Texas Instruments]
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OMAP3530, OMAP3525
SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013
www.ti.com
Table 6-129. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification
Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
MMC2
tW(clkL)
Typical pulse duration, output clk low
Y*PO(4)
Y*PO(4)
ns
tdc(clk)
Duty cycle error, output clk
125
125
ns
tj(clk)
Jitter standard deviation(5), output clk
200
200
ps
Standard MMC Mode
1/MMC
1/tc(clk)
Frequency(1), mmcx_ clk (2)
19.2
9.6
MHz
1
MMC2
tW(clkH)
Typical pulse duration, output clk high
X(3)*PO(4)
X(3)*PO(4)
ns
MMC2
tW(clkL)
Typical pulse duration, output clk low
Y*PO(4)
Y*PO(4)
ns
tdc(clk)
Duty cycle error, output clk
2604.2
5208.3
ps
tj(clk)
Jitter standard deviation(5), output clk
200
200
ps
MMC/SD/SDIO Interface 1 (1.8 V IO)
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
MMC5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc1_cmd transition
MMC6
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc1_datx transition
MMC/SD/SDIO Interface 1 (3.0 V IO)
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
MMC5
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc1_cmd transition
MMC6
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc1_datx transition
MMC/SD/SDIO Interface 2
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
MMC5
td(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc2_cmd transition
MMC6
td(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc2_datx transition
MMC/SD/SDIO Interface 3
tc(clk)
Rise time, output clk
10
10
ns
tW(clkH)
Fall time, output clk
10
10
ns
tW(clkL)
Rise time, output data
10
10
ns
tdc(clk)
Fall time, output data
10
10
ns
MMC5
td(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc3_cmd transition
MMC6
td(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to
4.3
47.8
4.3
99.9
ns
mmc3_datx transition
(5)
The jitter probability density can be approximated by a Gaussian function.
242
TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
Copyright © 2008–2013, Texas Instruments Incorporated
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