PC87364-XXXSLASHVLA datasheet(139/180 Pages) NSC

139 / 180 page

8.0 ACCESS.bus Interface (ACB) (Continued)

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8.2.3

Acknowledge (ACK) Cycle

The ACK cycle consists of two signals: the ACK clock pulse sent by the master with each byte transferred, and the ACK

signal sent by the receiving device (see Figure 24).

The master generates the ACK clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA

line (permits it to go high) to allow the receiver to send the ACK signal. The receiver must pull down the SDA line during the

ACK clock pulse, signalling that it has correctly received the last data byte and is ready to receive the next byte. Figure 25

illustrates the ACK cycle.

SDA

SCL

Start

Condition

Stop

Condition

Figure 23. Start and Stop Conditions

Start

Condition

Stop

Condition

SDA

SCL

MSB

ACK

12 3 - 6

3 - 8

Acknowledge

Signal From Receiver

Byte Complete

Interrupt Within

Receiver

Clock Line Held

Low by Receiver

While Interrupt

is Serviced

Figure 24. ACCESS.bus Data Transaction

Start

Condition

SCL

12 3 - 6

Transmitter Stays Off Bus

During Acknowledge Clock

Acknowledge

Signal From Receiver

Data Output

by Transmitter

Data Output

by Receiver

Figure 25. ACCESS.bus Acknowledge Cycle

PC87364-XXX/VLA 데이터시트(PDF) 139 Page - National Semiconductor (TI)

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