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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV2664FIBZWT 데이터시트(PDF) 211 Page - Texas Instruments |
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TNETV2664FIBZWT 데이터시트(HTML) 211 Page - Texas Instruments |
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211 / 249 page  TMS320C6424 www.ti.com SPRS347D – MARCH 2007 – REVISED DECEMBER 2009 Using the RMII Mode of the EMAC The EMAC contains logic that allows it to communicate using the Reduced Media Independent Interface (RMII) protocol. This logic must be taken out of reset before being used. To use the RMII mode of the EMAC follow these guidelines: • Supply a 50 MHz reference clock to the RMREFCLK input pin. • The PINMUX1 register RMII bit field must be programmed to "1" to select the RMII pins and the RMII mode of operation. • MACCONTROL.RMIISPEED must be programmed to the desired operating speed for the RMII interface. • MACCONTROL.FULLDUPLEX must be programmed to "1", selecting full duplex mode for RMII. 6.15.2 EMAC Peripheral Register Description(s) Table 6-55. Ethernet MAC (EMAC) Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 01C8 0000 TXIDVER Transmit Identification and Version Register 01C8 0004 TXCONTROL Transmit Control Register 01C8 0008 TXTEARDOWN Transmit Teardown Register 01C8 0010 RXIDVER Receive Identification and Version Register 01C8 0014 RXCONTROL Receive Control Register 01C8 0018 RXTEARDOWN Receive Teardown Register 01C8 0080 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register 01C8 0084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register 01C8 0088 TXINTMASKSET Transmit Interrupt Mask Set Register 01C8 008C TXINTMASKCLEAR Transmit Interrupt Mask Clear Register 01C8 0090 MACINVECTOR MAC Input Vector Register 01C8 00A0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register 01C8 00A4 RXINTSTATMASKED Receive Interrupt Status (Masked) Register 01C8 00A8 RXINTMASKSET Receive Interrupt Mask Set Register 01C8 00AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register 01C8 00B0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register 01C8 00B4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register 01C8 00B8 MACINTMASKSET MAC Interrupt Mask Set Register 01C8 00BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register 01C8 0100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register 01C8 0104 RXUNICASTSET Receive Unicast Enable Set Register 01C8 0108 RXUNICASTCLEAR Receive Unicast Clear Register 01C8 010C RXMAXLEN Receive Maximum Length Register 01C8 0110 RXBUFFEROFFSET Receive Buffer Offset Register 01C8 0114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register 01C8 0120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register 01C8 0124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register 01C8 0128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register 01C8 012C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register 01C8 0130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register 01C8 0134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register 01C8 0138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register 01C8 013C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register 01C8 0140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register Copyright © 2007–2009, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 211 Submit Documentation Feedback Product Folder Link(s): TMS320C6424 |
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