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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ENICSF2811PBKA 데이터시트(PDF) 135 Page - Texas Instruments |
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ENICSF2811PBKA 데이터시트(HTML) 135 Page - Texas Instruments |
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135 / 172 page  Lead Active Trail DIN t d(XCOH-XZCSL) t d(XCOH-XA) t d(XCOHL-XRDL) t d(XCOHL-XZCSH) t d(XCOHL-XRDH) WS (Synch) XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK XZCS0AND1 XZCS2 XZCS6AND7 , , XA[0:18] XRD XWE XR/W XD[0:15] XREADY(Synch) t h(XRDYsynchL) t su(XRDYsynchL)XCOHL t su(XD)XRD t a(XRD) t a(A) t h(XD)XRD t h(XRDYsynchH)XZCSH t su(XRDHsynchH)XCOHL See Note (E) = Don’t care. Signal can be high or low during this time. Legend: t e(XRDYsynchH) See Note (D) See Notes (A) and (B) See Note (C) TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 www.ti.com SPRS174T – APRIL 2001 – REVISED MAY 2012 A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle before an access to meet this requirement. B. During alignment cycles, all signals will transition to their inactive state. C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles. D. For each sample, setup time from the beginning of the access (D) can be calculated as: D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL E. Reference for the first sample is with respect to this point E = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the sample number (n = 1, 2, 3, and so forth). Figure 6-33. Example Read With Synchronous XREADY Access XTIMING register parameters used for this example: XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE 0 = XREADY ≥ 1 3 ≥ 1 1 0 N/A(1) N/A(1) N/A(1) (Synch) (1) N/A = “Don’t care” for this example Copyright © 2001–2012, Texas Instruments Incorporated Electrical Specifications 135 Submit Documentation Feedback Product Folder Link(s): TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812 |
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