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TNETV2685FIDZUT5 데이터시트(PDF) 125 Page - Texas Instruments |
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TNETV2685FIDZUT5 데이터시트(HTML) 125 Page - Texas Instruments |
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125 / 191 page ![]() 1 VPxCLKINx VPyCLKINy TMS320DM647 TMS320DM648 www.ti.com SPRS372H – MAY 2007 – REVISED APRIL 2012 6.11.3.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx) Table 6-54. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 6-31) -720<br Placement="li ne"/>-800<br Placement="li NO. UNIT ne"/>-900 -1100 MIN MAX 1 tskr(VKI) Skew rate, VPxCLKINx before VPyCLKINy ±500 ps Figure 6-31. Video Port Dual-Display Sync Timing Copyright © 2007–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 125 Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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