SPC56EL54X datasheet(108/165 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC56ELx, SPC564Lx

108/165

DocID15457 Rev 12

3.8

Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up

performance:



A supply overvoltage is applied to each power supply pin.



A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

3.9

Voltage regulator electrical characteristics

The voltage regulator is composed of the following blocks:



High power regulator HPREG1 (internal ballast to support core current)



High power regulator HPREG2 (external NPN to support core current)



Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO)



Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG)



Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH)



Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD)



Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN



High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD)



High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.



Power on Reset (POR)

HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when

external NPN transistor is present on board to supply core current. The SPC56XL60/54

always powers up using HPREG1 if an external NPN transistor is present. Then the

Table 17. ESD ratings(1), (2)

No.

Symbol

Parameter

Conditions

Class

Max value(3)

Unit

1VESD(HBM)

Electrostatic discharge



(Human Body Model)

TA = 25 °C

conforming to AEC-Q100-002

H1C

2000

2VESD(MM)

Electrostatic discharge



(Machine Model)

TA = 25 °C

conforming to AEC-Q100-003

200

3VESD(CDM)

Electrostatic discharge



(Charged Device Model)

TA = 25 °C

conforming to AEC-Q100-011

C3A

500

750 (corners)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification

requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at

room temperature followed by hot temperature, unless specified otherwise in the device specification.

3. Data based on characterization results, not tested in production.

Table 18. Latch-up results

No.

Symbol

Parameter

Conditions

Class

Static latch-up class

TA = 125 °C conforming to JESD 78

II level A

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