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SPC56EL54x 데이터시트(PDF) 126 Page - STMicroelectronics

부품명 SPC56EL54x
상세설명  Dual issue five-stage pipeline core
PDF  165 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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SPC56EL54x 데이터시트(HTML) 126 Page - STMicroelectronics

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Electrical characteristics
SPC56ELx, SPC564Lx
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DocID15457 Rev 12
2. Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for <100
program/erase cycles, nominal supply values and operation at 25°C. These values are verified at production test.
3. Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product life. These
values are characterized, but not tested.
4. Program times are actual hardware programming times and do not include software overhead.
Table 29. Flash memory timing
Symbol
Parameter
Value
Unit
Min
Typ
Max
TRES
D
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low
——
100
ns
TDONE
D
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared
——
5
ns
TPSRT
D
Time between program suspend resume and the next program
suspend request.(1)
100
—
—
µs
TESRT
D
Time between erase suspend resume and the next erase
suspend request.(2)
10
ms
1. Repeated suspends at a high frequency may result in the operation timing out, and the flash module will respond by
completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish (MCR[DONE] = 1 during
Program operation). The minimum time between suspends to ensure this does not occur is TPSRT.
2. If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs during erase pulse. This improves erase
time but reduces cycling figure due to overstress.
Table 30. Flash memory module life
No.
Symbol
Parameter
Value
Unit
Minimum
Typical Maximum
1P/E
C
Number of program/erase cycles per block for 16 KB,
48 KB, and 64 KB blocks over the operating
temperature range(1)
100000
—
—
cycles
2P/E
C
Number of program/erase cycles per block for 128 KB
and 256 KB blocks over the operating temperature
range(1)
1000
100000
(2)
—
cycles
3
Retenti
on
C
Minimum data retention at 85 °C average ambient
temperature(3)
Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
20
10
5
—
—
—
—
—
—
years
1. Operating temperature range is TJ from –40 °C to 150 °C. Typical endurance is evaluated at 25 C.
2. Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks.
3. Ambient temperature averaged over duration of application, not to exceed product operating temperature range.



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