ST72344K2 datasheet(158/247 Pages) STMICROELECTRONICS

158 / 247 page

On-chip peripherals

ST72344xx, ST2345xx

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Doc ID 12321 Rev 6

EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example

PE=1).

EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.

11.6.5

Low-power modes

11.6.6

Interrupts

Figure 70.

Event flags and interrupt generation

Table 64.

Mode description

Mode

Description

Wait

No effect on I2C interface.

I2C interrupts cause the device to exit from Wait mode.

Halt

I2C registers are frozen.

In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus.

The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit

from HALT mode” capability.

Table 65.

Interrupt events (1)

Interrupt event

Event flag

Enable

control bit

Exit from

Wait

Exit from

Halt

10-bit address sent event (Master mode)

ADD10

ITE

Yes

End of byte transfer event

BTF

Yes

Address matched event (Slave mode)

ADSL

Yes

Start bit generation event (Master mode)

Yes

Acknowledge failure event

Yes

Stop detection event (Slave mode)

STOPF

Yes

Arbitration lost event (Multimaster configuration)

ARLO

Yes

Bus error event

BERR

Yes

BTF

ADSL

STOPF

ARLO

BERR

EVF

Interrupt

ITE

* EVF can also be set by EV6 or an error from the SR2 register.

ADD10

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