ST72344K2 datasheet(202/247 Pages) STMICROELECTRONICS

202 / 247 page

Electrical characteristics

ST72344xx, ST2345xx

202/247

Doc ID 12321 Rev 6

13.3

Operating conditions

Note:

When the power supply is between 2.7 and 2.95 V (VIT+(LVD) max), the device is either in the

guaranteed functional area or in reset state, thus allowing a deterministic application

behavior. However, the LVD may generate a reset below 2.95 V and the user should

therefore not use the device below this level when the LVD is enabled.

Figure 87.

fCPU maximum operating frequency versus VDD supply voltage

Table 87.

General operating conditions (1)

TA = -40 to +85 °C unless otherwise specified.

Symbol

Parameter

Conditions

Min

Max

Unit

VDD

Supply voltage

fCPU = 8 MHz. max.

3.3

5.5

fCPU = 4 MHz. max.

2.7

5.5

fOSC

External clock frequency

3.3 V

≤V

DD≤ 5.5 V

Up to 16

MHz

2.7 V

≤ V

DD < 3.3 V

Up to 8

Table 88.

LVD thresholds

Symbol

Parameter

Conditions (1)

TA = -40 to +85 °C unless otherwise specified.

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High threshold

Med. threshold

Low threshold

3.85

3.24

2.60

4.20

3.56

2.88

4.61

3.90

3.14

VIT-(LVD)

Reset generation threshold

(VDD fall)

High threshold

Med. threshold

Low threshold

3.66

3.04

2.45

3.98

3.36

2.71

4.36

3.66

2.95

Vhys(LVD)

LVD voltage threshold

hysteresis

VIT+(LVD)-VIT-(LVD)

200

VtPOR

VDD rise time rate

20 (2)

Not tested in production, guaranteed by design

100 (2)

ms/V

tg(VDD)

VDD glitches filtered by LVD

150

fCPU [MHz]

SUPPLY VOLTAGE [V]

4.0

4.5

5.0

FUNCTIONALITY

NOT GUARANTEED

IN THIS AREA

5.5

3.6

FUNCTIONALITY

GUARANTEED

IN THIS AREA

3.3

2.7

CAUTION: RESET MAY

BE ACTIVATED BY LVD

IN THIS AREA

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