ST72361AR4-Auto datasheet(170/279 Pages) STMICROELECTRONICS

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LINSCI serial communication interface (LIN master/slave)

ST72361xx-Auto

170/279

Doc ID 12468 Rev 3

Bit 6 = TCIE Transmission complete interrupt enable

This bit is set and cleared by software.

0: interrupt is inhibited

1: an SCI interrupt is generated whenever TC = 1 in the SCISR register

Bit 5 = RIE Receiver interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: an SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register

Bit 4 = ILIE Idle line interrupt enable.

This bit is set and cleared by software.

0: interrupt is inhibited

1: an SCI interrupt is generated whenever IDLE = 1 in the SCISR register.

Bit 3 = TE Transmitter enable.

This bit enables the transmitter. It is set and cleared by software.

0: transmitter is disabled

1: transmitter is enabled

Note:

During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle

line) after the current word.

When TE is set there is a 1 bit-time delay before the transmission starts.

Bit 2 = RE Receiver enable.

This bit enables the receiver. It is set and cleared by software.

0: receiver is disabled in the SCISR register

1: receiver is enabled and begins searching for a start bit

Bit 1 = RWU Receiver wake-up.

This bit determines if the SCI is in mute mode or not. It is set and cleared by software and

can be cleared by hardware when a wake-up sequence is recognized.

0: receiver in active mode

1: receiver in mute mode

Note:

Before selecting Mute mode (by setting the RWU bit) the SCI must first receive a data byte,

otherwise it cannot function in Mute mode with wakeup by Idle line detection.

In address mark detection wake-up configuration (WAKE bit = 1) the RWU bit cannot be

modified by software while the RDRF bit is set.

Bit 0 = SBK Send break.

This bit set is used to send break characters. It is set and cleared by software.

0: no break character is transmitted

1: break characters are transmitted

Note:

If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end

of the current word.

15.8.4

Data register (SCIDR)

Read/ write

Reset value: Undefined

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