ST72361AR4-Auto datasheet(186/279 Pages) STMICROELECTRONICS

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LINSCI serial communication interface (LIN master/slave)

ST72361xx-Auto

186/279

Doc ID 12468 Rev 3

15.10.4

Control register 3 (SCICR3)

Read/ write

Reset value: 0000 0000 (00h)

Bit 7 = LDUM LIN Divider Update Method.

This bit is set and cleared by software and is also cleared by hardware (when RDRF = 1). It

is only used in LIN Slave mode. It determines how the LIN Divider can be updated by

software.

0: LDIV is updated as soon as LPR is written (if no auto synchronization update occurs

at the same time).

1: LDIV is updated at the next received character (when RDRF = 1) after a write to the

LPR register

Note:

If no write to LPR is performed between the setting of LDUM bit and the reception of the

next character, LDIV will be updated with the old value.

After LDUM has been set, it is possible to reset the LDUM bit by software. In this case, LDIV

can be modified by writing into LPR / LPFR registers.

Bits 6:5 = LINE, LSLV LIN Mode Enable Bits.

These bits configure the LIN mode:

The LIN master configuration enables:

The capability to send LIN synch breaks (13 low bits) using the SBK bit in the SCICR2

The LIN slave configuration enables:

●

The LIN slave baud rate generator. The LIN Divider (LDIV) is then represented by the

LPR and LPFR registers. The LPR and LPFR registers are read/write accessible at the

address of the SCIBRR register and the address of the SCIETPR register

●

Management of LIN headers.

●

LIN synch break detection (11-bit dominant).

●

LIN wake-up method (see LHDM bit) instead of the normal SCI Wake-Up method.

●

Inhibition of break transmission capability (SBK has no effect)

●

LIN parity checking (in conjunction with the PCE bit)

LDUM

LINE

LSLV

LASE

LHDM

LHIE

LHDF

LSF

Table 66.

LIN mode configuration

LINE

LSLV

Meaning

LIN mode disabled

LIN Master Mode

LIN Slave Mode

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