| 전자부품 데이터시트 검색엔진 |
|
ST72361AR4-Auto 데이터시트(PDF) 263 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST72361AR4-Auto 데이터시트(HTML) 263 Page - STMicroelectronics |
|
263 / 279 page ![]() ST72361xx-Auto Device configuration and ordering information Doc ID 12468 Rev 3 263/279 OPT1 = reserved OPT0 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles inserted during the RESET phase and when exiting HALT mode. For resonator oscillators, it is advised to select 4096 due to the long crystal stabilization time. 0: reset phase with 4096 CPU cycles 1: reset phase with 256 CPU cycles MS 4~8 MHz 1 0 HS 8~16 MHz 1 Table 119. OSCRANGE selection (continued) Typical frequency range OSCRANGE 10 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |