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STM32F769AI 데이터시트(PDF) 195 Page - STMicroelectronics

부품명 STM32F769AI
상세설명  Dual mode Quad-SPI
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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STM32F769AI 데이터시트(HTML) 195 Page - STMicroelectronics

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STM32F765xx STM32F767xx STM32F768Ax STM32F769xx
Electrical characteristics
224
The MDIO controller is mapped on APB2 domain. The frequency of the APB bus should at
least 1.5 times the MDC frequency: FPCLK2 ≥ 1.5 * FMDC
Figure 60. MDIO Slave timing diagram
CAN (controller area network) interface
Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate
function characteristics (CANx_TX and CANx_RX).
5.3.30
FMC characteristics
Unless otherwise specified, the parameters given in Table 100 to Table 113 for the FMC
interface are derived from tests performed under the ambient temperature, fHCLK frequency
and VDD supply voltage conditions summarized in Table 17, with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Measurement points are done at CMOS levels: 0.5VDD
1. Guaranteed by characterization results.
Table 99. MDIO Slave timing parameters
Symbol
Parameter
Min
Typ
Max
Unit
FsDC
Management Data clock
-
-
40
MHz
td(MDIO)
Management Data input/output output valid time
78
20
ns
tsu(MDIO) Management Data input/output setup time
4-
-
th(MDIO)
Management Data input/output hold time
1-
-



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