STM32F769AI datasheet(220/255 Pages) STMICROELECTRONICS

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Electrical characteristics

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DocID029041 Rev 4

5.3.34

Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 122 for DFSDM are derived from

tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage

summarized in Table 17, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30pF

•

Measurement points are done at CMOS levels: 0.5 x VDD

Refer to Section 5.3.20: I/O port characteristics for more details on the input/output alternate

function characteristics (DFSDM1_CKINx, DFSDM1_DATINx, DFSDM1_CKOUT for

DFSDM1).

Table 122. DFSDM measured timing 1.71-3.6V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fDFSDMCLK

DFSDM clock

1.71 < VDD < 3.6 V

fSYSCLK

MHz

fCKIN

(1/TCKIN)

Input clock

frequency

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

1.71 < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

External clock mode

(SPICKSEL[1:0]=0),

2.7 < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

1.71 < VDD < 3.6 V

(fDFSDMCLK/4)

SPI mode (SITP[1:0]=0,1),

Internal clock mode

(SPICKSEL[1:0]

≠0),

2.7 < VDD < 3.6 V

(fDFSDMCLK/4)

fCKOUT

Output clock

frequency

1.71 < VDD < 3.6 V

DuCyCKOUT

Output clock

frequency duty

cycle

1.71 < VDD < 3.6 V

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