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N575C145 데이터시트(PDF) 8 Page - List of Unclassifed Manufacturers

부품명 N575C145
상세설명  system-on-chip product optimized
PDF  23 Pages
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N575C145 Data Sheet
Release Date: Sept, 2015
- 8 -
Version A1.0
Pad No.
Pad Name
Type
Alt CFG
Description
Chip
7
PB.2
A/I/O
0
General purpose input/output, analog capable; Port B, bit
2
I
2C_SCL
I/O
1
Serial Clock,
I
2C interface
CMP2
AIO
2
Configure as relaxation oscillator for capacitive touch
sensing
SPI_SCLK
I/O
3
Serial Clock for SPI interface
8
PB.1
A/I/O
0
General purpose input/output, analog capable; Port B, bit
1. Triggers external interrupt 1 (EINT1/IRQ3)
MCLK
O
1
Master clock output for synchronizing external device
CMP1
AIO
2
Configure as relaxation oscillator for capacitive touch
sensing
SPI_SSB1
O
3
Slave Select Bar 1 for SPI interface
9
PB.0
A/I/O
0
General purpose input/output, analog capable; Port B, bit
0. Triggers external interrupt 0 (EINT0/IRQ2)
SPI_SSB1
O
3
Slave Select Bar 1 for SPI interface
CMP0
AIO
2
Configure as relaxation oscillator for capacitive touch
sensing
SPI_SSB0
I/O
3
Slave Select Bar 0 for SPI interface
10
11
Reserved
Remain unconnected
12
VCCDPST
P
Digital Supply for Chip, Connect to VCCD
13
VCCD
P
Main Digital Supply for Chip. Supplies all IO except
analog, Speaker Driver and PA<7:0>
14
VREG
P
Logic regulator output for decoupling. A 1µF capacitor
returning to VSSD must be placed on it..
15
PA.15
I/O
0
General purpose input/output; Port A, bit 15
TM1
I
1
External input to Timer 1
SDIN
I
2
Sigma-Delta bit stream input for digital MIC mode
16
PA.9
I/O
0
General purpose input/output; Port A, bit 9
UART_RX
I
1
Receive channel of UART
I
2S_BCLK
I/O
2
Bit Clock for
I
2S interface
17
PA.8
I/O
0
General purpose input/output; Port A, bit 8


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