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N575F145 데이터시트(PDF) 8 Page - List of Unclassifed Manufacturers |
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N575F145 데이터시트(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 21 page ![]() N575F145 Data Sheet Release Date: Sep. 2015 - 8 - Version A1.1 Pin Name Pin Type Alt CFG Description CMP2 AIO 2 Configure as relaxation oscillator for capacitive touch sensing SPI_SCLK I/O 3 Serial Clock for SPI interface PB.1 A/I/O 0 General purpose input/output pin, analog capable; Port B, bit 1. Triggers external interrupt 1 (EINT1/IRQ3) MCLK O 1 Master clock output for synchronizing external device CMP1 AIO 2 Configure as relaxation oscillator for capacitive touch sensing SPI_SSB1 O 3 Slave Select Bar 1 for SPI interface PB.0 A/I/O 0 General purpose input/output pin, analog capable; Port B, bit 0. Triggers external interrupt 0 (EINT0/IRQ2) SPI_SSB1 O 3 Slave Select Bar 1 for SPI interface CMP0 AIO 2 Configure as relaxation oscillator for capacitive touch sensing SPI_SSB0 I/O 3 Slave Select Bar 0 for SPI interface VCCD P Main Digital Supply for Chip. Supplies all IO except analog, Speaker Driver and PA<7:0> VREG P Logic regulator output decoupling pin. A 1µF capacitor returning to VSSD must be placed on this pin. NC Should remain unconnected. NC Should remain unconnected. PA.15 I/O 0 General purpose input/output pin; Port A, bit 15 TM1 I 1 External input to Timer 1 SDIN I 2 Sigma Delta bit stream input for digital MIC mode PA.9 I/O 0 General purpose input/output pin; Port A, bit 9 UART_RX I 1 Receive channel of UART I 2S_BCLK I/O 2 Bit Clock for I 2S interface PA.8 I/O 0 General purpose input/output pin; Port A, bit 8 UART_TX O 1 Transmit channel of UART I 2S_FS I/O 2 Frame Sync Clock for I 2S interface VCCSPK P Power Supply for PWM Speaker Driver SPK+ O Positive Speaker Driver Output VSSSPK P Ground for PWM Speaker Driver SPK- O Negative Speaker Driver Output |
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