The **ADCMP601** is a very fast, single-supply comparator designed by Analog Devices. It is part of a family of high-speed comparators characterized by their small footprint and high efficiency. --- ## 1. Key Specifications The ADCMP601 is primarily defined by its speed and low power consumption. | Parameter | Specification | |:---|:---| | **Propagation Delay** | 3.5 ns (typical) | | **Supply Voltage** | 2.5 V to 5.5 V | | **Output Type** | CMOS/TTL Compatible | | **Supply Current** | 3 mA (typical) | | **Package** | SC70-6 | | **Input Common-Mode Range** | -0.2 V to VCC + 0.2 V | --- ## 2. Core Electronic Components & Features ### A. High-Speed Architecture The device uses a specialized high-speed stage that allows for a **3.5 ns propagation delay**. This makes it ideal for timing-critical applications like clock recovery or pulse-width modulation (PWM) signal processing. ### B. Rail-to-Rail Input Stage The ADCMP601 features a rail-to-rail input stage. This means the input voltage can swing slightly above the positive supply and slightly below the negative supply (ground) without damaging the part or causing phase reversal. ### C. CMOS/TTL Compatible Output The output stage is designed to interface directly with standard digital logic: * **High Logic:** Near $V_{CC}$ * **Low Logic:** Near $GND$ * It is capable of driving high-speed digital gates or FPGA pins without additional level-shifting components. ### D. Integrated Hysteresis To prevent "chattering" (rapid oscillations when the input signal is noisy and close to the threshold), the ADCMP601 includes internal hysteresis. This ensures a clean, single transition for every crossing of the threshold. --- ## 3. Pin Configuration | Pin No. | Name | Function | |:---:|:---|:---| | 1 | $V_{OUT}$ | Digital Output | | 2 | $V_{EE}$ | Negative Supply / Ground | | 3 | $V_{IN+}$ | Non-inverting Input | | 4 | $V_{IN-}$ | Inverting Input | | 5 | $LE/CAN$ | Latch Enable (allows the output to be "frozen") | | 6 | $V_{CC}$ | Positive Supply | --- ## 4. Typical Application Circuit Below is a simple representation of how the ADCMP601 is used as a zero-crossing detector. ```c VCC (3.3V) ---- [0.1uF Cap] ---- Pin 6 (VCC) | Signal In ---- Pin 3 (VIN+) [ADCMP601] ---- Pin 1 (VOUT) ---- To MCU/FPGA | Reference ---- Pin 4 (VIN-) | (e.g. GND) | Pin 2 (VEE/GND) ```