The **M24C04-RDS3TP** is a specific variant of the M24C04 family of I²C Serial EEPROM (Electrically Erasable Programmable Read-Only Memory) chips manufactured by STMicroelectronics. Below is a breakdown of its technical specifications, pinout, and key features. --- ## 1. Technical Specifications | Parameter | Specification | | :--- | :--- | | **Memory Size** | 4 Kbit (512 bytes) | | **Organization** | 2 blocks of 256 bytes (512 x 8 bits) | | **Interface** | I²C (Inter-Integrated Circuit) | | **Operating Voltage** | 1.8V to 5.5V | | **Clock Frequency** | 400 kHz (Fast Mode) or 1 MHz (Fast Mode Plus) | | **Write Cycles** | More than 4 million cycles | | **Data Retention** | More than 200 years | | **Package Type** | TSSOP8 (Thin Shrink Small Outline Package) | | **Temperature Range** | -40°C to +125°C (Automotive grade compliant) | --- ## 2. Part Number Breakdown: M24C04-RDS3TP Understanding the suffix is crucial for identifying the specific physical and electrical traits: * **M24**: I²C Serial Access EEPROM. * **C04**: 4 Kbit capacity. * **-R**: Range of operating voltage (1.8V to 5.5V). * **D**: Device process/Generation. * **S**: TSSOP8 package (3 x 4.4 mm body). * **3**: Range 3 temperature (-40 to +125 °C). * **TP**: Tape and Reel packaging. --- ## 3. Pin Configuration (TSSOP8) ```text +---U---+ E1 | 1 8 | VCC E2 | 2 7 | WC (Write Control) E3 | 3 6 | SCL VSS | 4 5 | SDA +-------+ ``` ### Pin Descriptions: * **E1, E2**: Chip Address inputs. These allow multiple devices to be connected to the same I²C bus. (Note: In a 4Kbit chip, E0 is often used internally for page addressing). * **SDA (Serial Data)**: Bi-directional pin used to transfer data in and out. * **SCL (Serial Clock)**: Synchronizes the data transfer. * **WC (Write Control)**: A hardware protection pin. If connected to $V_{CC}$, write operations are inhibited. If connected to $V_{SS}$ (Ground), write operations are enabled. * **VCC/VSS**: Power supply and Ground. --- ## 4. Key Operational Features ### I²C Addressing The M24C04 uses a 7-bit device address. Because it is a 4 Kbit device, it is divided into two 256-byte blocks. The address includes: 1. **Device Type Identifier**: `1010` (Fixed for EEPROMs). 2. **Chip Enable Bits**: Defined by the physical state of pins E1 and E2. 3. **Block Select Bit**: Used to choose between the upper or lower 256-byte halves. ### Write Protection The device features a hardware "Write Control" (WC) pin. This is highly useful in embedded systems to prevent accidental data corruption during power-up or software glitches by physically tying the pin to a high logic level until a write is intentionally required. ### Byte and Page Write * **Byte Write**: Write a single byte to a specific address. * **Page Write**: Write up to 16 bytes in a single bus cycle, significantly increasing throughput for larger data sets.