The **PLL602-39OC-R** is a high-performance, low-phase-noise Frequency Multiplier IC developed by PhaseLink (now part of Microchip Technology). It is specifically designed to work with high-frequency crystals to produce a clean LVPECL output. --- ## 1. Technical Specifications The following table summarizes the core electrical characteristics of the device: | Feature | Specification | | :--- | :--- | | **Output Type** | Differential LVPECL | | **Input Frequency Range** | 17MHz to 33.3MHz (Crystal or Reference) | | **Output Frequency Range** | 68MHz to 133.3MHz (4x Multiplier) | | **Operating Voltage** | 2.5V or 3.3V (±10%) | | **Phase Jitter** | < 0.5ps RMS (12kHz to 20MHz) | | **Operating Temperature** | 0°C to 70°C (Commercial Grade) | | **Package** | TSSOP-8L or SOIC-8L | --- ## 2. Key Components & Architecture The IC functions as a specialized Phase-Locked Loop (PLL). Below are the primary internal electronic sections: ### A. Reference Input Section The device contains an on-chip oscillator circuit. You can connect a fundamental mode parallel resonant crystal across the `XIN` and `XOUT` pins. Alternatively, it can accept a standard CMOS reference clock. ### B. Phase-Locked Loop (PLL) * **Phase Frequency Detector (PFD):** Compares the input frequency with the feedback signal. * **Voltage Controlled Oscillator (VCO):** Operates at high frequencies to ensure low jitter. * **Multiplier:** Specifically tuned for a **4x multiplication factor** (e.g., a 25MHz crystal produces a 100MHz output). ### C. Output Driver (LVPECL) The output stage is a **Low-Voltage Positive Emitter-Coupled Logic (LVPECL)** driver. * It provides differential outputs (`OUTP` and `OUTN`). * LVPECL is preferred in high-speed systems (like Ethernet or Fiber Channel) because of its excellent noise immunity and high-speed switching capabilities. --- ## 3. Pin Configuration | Pin Number | Pin Name | Description | | :--- | :--- | :--- | | 1 | XIN | Crystal Input or Reference Clock | | 2 | XOUT | Crystal Output (Leave floating if using Ref Clock) | | 3 | VDD | Power Supply (2.5V / 3.3V) | | 4 | VSS | Ground | | 5 | OUTP | Positive LVPECL Output | | 6 | OUTN | Negative LVPECL Output | | 7 | OE | Output Enable (Active High) | | 8 | NC/FIN | No Connect or Factory Test Pin | --- ## 4. Application Circuit Considerations When designing with the PLL602-39OC-R, keep the following electronic principles in mind: 1. **Termination:** LVPECL outputs require proper termination (typically 50Ω to $V_{DD} - 2V$) to ensure signal integrity and prevent reflections. 2. **Decoupling:** Place a 0.01µF and a 0.1µF ceramic capacitor as close to the `VDD` pin as possible to filter power supply noise, which directly impacts jitter performance. 3. **Crystal Selection:** Use a crystal with a load capacitance ($C_L$) matching the IC’s specifications (usually 18pF) to ensure frequency accuracy.