MPEG-4 Video Decoder LSI

Features
□ A single-chip MPEG-4 video decoder LSI performs 15frames/sec of MPEG-4 video decoding with QCIF (176x144 pixels) at 30MHz clock frequency.
□ A 4-Mbit embedded DRAM is integrated to reduce power consumption without performance degradation.
□ An MPEG-4 video core consists of a 16-bit RISC processor and dedicated hardware accelerators so as to bring programmability, high performance, and low power consumption.
□ Firmware program for the RISC is downloaded into the embedded DRAM before starting operation. Other applications, such as H.263, are performed by using appropriate firmware.
□ General host interface is adopted in order to support various host CPU.