DESCRIPTIONS
The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The PLL can be bypassed for test purposes by strapping AVdd to ground.

FEATURES
• PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
• Distributes one clock Input to one bank of ten differential outputs.
• Track spread spectrum clocking for EMI reduction.
• Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming CLKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled.
• Four independent programmable DDR skew channels from –0.3ns to +0.4ns with step size ±100ps.
• Support 2-wire I2C serial bus interface.
• 2.5V Operating Voltage.
• Available in 48-Pin 300mil SSOP.