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VSC9142 데이터시트 (PDF) - Vitesse Semiconductor Corporation

VSC9142 Datasheet PDF - Vitesse Semiconductor Corporation
부품명 VSC9142
다운로드  VSC9142 다운로드
파일 크기   249.87 Kbytes
페이지   30 Pages
제조업체  VITESSE [Vitesse Semiconductor Corporation]
홈페이지  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation
상세설명 SONET/SDH 2.5Gbps Transport Terminating Transceiver

VSC9142 Datasheet (PDF)

Go To PDF Page 다운로드 데이터시트
VSC9142 Datasheet PDF - Vitesse Semiconductor Corporation

부품명 VSC9142
다운로드  VSC9142 Click to download

파일 크기   249.87 Kbytes
페이지   30 Pages
제조업체  VITESSE [Vitesse Semiconductor Corporation]
홈페이지  http://www.vitesse.com
Logo VITESSE - Vitesse Semiconductor Corporation
상세설명 SONET/SDH 2.5Gbps Transport Terminating Transceiver

VSC9142 데이터시트 (HTML) - Vitesse Semiconductor Corporation


VSC9142 제품 세부 정보

Functional Overview
The VSC9142 is a dual mode SONET/SDH to Packet/ATM framing device that integrates the physical layer components of 2.5 Gbps clock and data recovery and serialization/deserialization into a single device. In the Packet over SONET (POS) mode, this device can be used in equipment interconnecting IP/PPP/HDLC data over public or private SONET/SDH networks. Similarly, in the ATM over SONET (ATM) mode, this device can be used in equipment interconnecting ATM switches. In addition, the VSC9142 can be used in various applications involving LAPS (X.85/Y.1321) and Ethernet over SONET/SDH protocols.

Features
• Dual Mode STS-48c/STM-16c to Packet/ATM Framing Device for User Network Interface and Network Node Interface Applications
• Integrated 2.5 Gbps Clock and Data Recovery and Serial Clock and Data Output with Power-Down Feature
• Selectable Reference Clock Frequencies and Sources for Transmit and Receive datapaths
• Terminates and Generates Full SONET/SDH Section, Line, and Path Layers
• Dedictated Ports for Section/Line Overhead Access (Extraction/Insertion)
• Extensive SONET/Packet/Cell Performance Monitoring Features
• Programmable Packet/Cell Filtering and Discarding Functionalities
• Industry Compliant Drop Side Packet/Cell Interface for Single-PHY Applications
• 4-bit OIF Compliant Line Interface to be usedfor STS-192 applications
• +1.8V and +3.3V Power Supplies
• Compliant with SONET and SDH Requirements as Stated in ANSI T1.105, Bellcore GR-253-CORE and ITU-T G.707 Documents
• Compliant with PPP in HDLC-like Framing and Mapping into SONET/SDH as Defined in IETF RDFC 1619/1661/1662/2615




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