DESCRIPTION
The TC511001AP/AJ/AZ is the new generation dynamic RAM organized 1,048,576 words by
1 bit. The TC511001AP/AJ/AZ utilizes TOSHIBA's CMOS Silicon gate process technology as
well as advanced circuit techniques to provide wide operating margins, both internally
and to the system user. Multiplexed address inputs permit the TC511001AP/AJ/AZ to be
packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic
ZIP. The package size provides high system bit densities and is compatible with widely
available automated testing and insertion equipment. System oriented features include
single power supply of 5V±10% tolerance, direct interfacing capability with high perform-
ance logic families such as Schottky TTL. The special feature of TC511001AP/AJ/AZ is
nibble mode, allowing the user to serially access 4 bits of data at a high data rate.

FEATURES
1,048,576 word by 1 bit organization
Fast access time and cycle time.
FRAC RAS Access Time
CAA
Column Address
Access Time
CAS Access Time
Cycle Time
Nibble Mode
ENCAC Access Time
CAC
ERC
Nibble Mode
*NC Cycle Time
FO$11001AB/AJ/A-73-80/-10
70ns 80ns 100ns
35ns
40ns 50ns
20ns 20ns 25ns
130ns 150ns 180ns
20ns 20ns 20ns
40ns
40ns 40ns
Single power supply of 5V±10% with a
built-in VBB generator
Low Power:
440mW MAX. Operating (TC511001AP/AJ/AZ-70)
385mW MAX. Operating (TC511001AP/AJ/AZ-80)
330ml MAX. Operating (TC511001AP/AJ/AZ-10)
5.5mW MAX. Standby
Output unlatched at cycle end allows two-
dimensional chip selection
Common I/O capability using "EARLY WRITE"
operation
Read-Modify-Write,
CAS before RAS refresh,
RAS-only refresh, Hidden refresh, Nibble
Mode and Test Mode capability
All inputs and output TTL compatible
512 refresh cycles/8ms
Package
Plastic DIP: TC511001AP
Plastic SOJ: TC511001AJ
Plastic ZIP: TC511001AZ