Intel® Stratix® 10 TX FPGAs feature power-efficient, dual-mode transceivers, capable
of both 57.8 Gbps PAM4 (Pulse Amplitude Modulation) and 28.9 Gbps NRZ (Non
Return to Zero) operation. Supported by hardened PCI Express Gen 3 and 10/25/100
Gbps Ethernet MAC IP blocks, these devices can deliver over 8 Tbps of aggregate
bandwidth, meeting the demanding transceiver bandwidth and power budget
specifications of next generation designs.
In addition to the 57.8 Gbps PAM4 / 28.9 Gbps NRZ dual-mode transceivers, Intel
Stratix 10 TX devices feature several other breakthrough innovations. These include
all new HyperFlex® core architecture, hardened floating point DSP blocks, hardened
external memory controllers and advanced packaging technology based on Intel's
Embedded Multi-die Interconnect Bridge (EMIB).
With an embedded quad-core 64-bit Arm* Cortex*-A53 hard processor system (HPS)
available in select devices, Intel Stratix 10 TX FPGAs deliver power efficient,
application-class processing, and allow designers to extend hardware virtualization
into the FPGA fabric.
Intel Stratix 10 TX FPGAs integrate a monolithic 14 nm FPGA fabric die with multiple
high-speed transceiver tiles, all inside a single flip-chip BGA package. This
implementation, combined with the unmatched transceiver bandwidth and core fabric
performance, demonstrates Intel's commitment to deliver high-performance
programmable solutions to your most challenging system design problems.
Important innovations in Intel Stratix 10 TX devices include:
• All new Intel Hyperflex™ core architecture delivering 2X the core performance
compared to previous generation high-performance FPGAs
• Intel 14 nm tri-gate (FinFET) technology
• Heterogeneous 3D System-in-Package (SiP) technology
• Monolithic core fabric with up to 2.8 million logic elements (LEs)
• Up to 144 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles
• Transceiver data rates up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ for chip-to-chip,
chip-to-module, and backplane applications
• Embedded eSRAM (47.25 Mbit) in select devices, and M20K (20 Kb) internal SRAM
memory blocks
• Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops
(PLLs)
• Hard PCI Express® Gen3 x16 intellectual property (IP) blocks
• Hard 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ
signals (528, 514) and PAM4 signals (544, 514)