Description
The STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL. The device recognizes the CCP 32bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 52 MHz) is transmitted in parallel with data. Input and Output data are rising edge strobe. This chipset is an ideal means to link mobile camera modules to baseband processors. In order to minimize static current consumption, it is possible to shut down the device when the interface is not being used by a power-down (EN) pin that reduces to 10µA the Maximum Current Consumption making this device ideal for portable applications like Mobile Phone, Portable Battery Equipment. Two dedicated I2C lines are provided to translate bidirectional controls from camera and µC devices. The STCCP27A is offered in a µTFBGA