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QL3025 데이터시트 (PDF) - List of Unclassifed Manufacturers

QL3025 Datasheet PDF - List of Unclassifed Manufacturers
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부품 상세설명 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QL3025 Datasheet (PDF)

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QL3025 Datasheet PDF - List of Unclassifed Manufacturers

부품명 QL3025
다운로드  QL3025 Click to view

파일 크기   528.06 Kbytes
페이지   17 Pages
제조업체  ETC1 [List of Unclassifed Manufacturers]
홈페이지  
Logo ETC1 - List of Unclassifed Manufacturers
부품 상세설명 25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QL3025 데이터시트 (HTML) - List of Unclassifed Manufacturers

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QL3025 제품 세부 정보

[QUICK LOGIC]

Product Summary
The pASIC 3 FPGA family features up to 60,000 usable PLD gates. pASIC 3 FPGAs are fabricated on a 0.35mm four-layer metal process using Quick Logic’s patented ViaLink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.

Device Highlights
High Performance and High Density
■60,000 Usable PLD Gates with 316 I/Os
■16-bit counter speeds over 300 MHZ, data path speeds over 400 MHz
■0.35um four-layer metal non-volatile CMOS process for smallest die sizes

Easy to Use/Fast Development Cycles
■100% routable with 100% utilization and complete pin-out stability
■Variable-grain logic cells provide high performance and 100% utilization
■Comprehensive design tools include high quality Verilog/VHDL synthesis

Advanced I/O Capabilities
■Interfaces with both 3.3 volt and 5.0 volt devices
■PCI compliant with 3.3V and 5.0V buses for -1/-2 speed grades
■Full JTAG boundary scan
■Registered I/O cells with individually controlled clocks and output enables

Features
Total of 180 I/O pins
■308 bidirectional input/output pins, PCI-compliant for 5.0 volt and 3.3 volt buses for -1/-2 speed grades
■8 high-drive input/distributed network pins Eight Low-Skew Distributed Networks
■Two array clock/control networks available to the logic cell flip-flop clock, set and reset inputs - each
driven by an input-only pin
■Up to six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback High Performance
■Input + logic cell + output total delays under 6 ns
■Data path speeds exceeding 400 MHz
■Counter speeds over 300 MHz



유사한 부품 번호 - QL3025

제조업체부품명데이터시트부품 상세설명
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유사한 설명 - QL3025

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