Features
▪ Close-in phase noise complies with Common Public Radio
Interface (CPRI) frequency synchronization requirements
▪ Supports all ITU-T G.709 frequencies
▪ Meets OTN jitter and wander requirements per ITU-T G.8251
▪ Four independent DPLL/DCO channels
• Each can act as a frequency synthesizer, jitter attenuator,
Digitally Controlled Oscillator (DCO), or Digital Phase Lock
Loop (DPLL)
• DPLL Digital Loop Filters (DLFs) are programmable with
cut-off frequencies from 1.1Hz to 22kHz
• Generate output frequencies that are independent of input
frequencies via a Fractional Output Divider (FOD)
• Each FOD supports output phase tuning with 50ps
resolution
▪ Four independent DCO channels
• Each DCO can act as an independent DCO or as a Satellite
Channel
• Satellite Channels are associated with a source DPLL or
DCO to increase the number of independently
programmable FODs and output stages available to the
source channel
• Each DCO generates an independent output frequency via a
Fractional Output Divider (FOD)
▪ 12 differential / 24 LVCMOS outputs
• Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)
• Jitter below 150fs RMS (10kHz to 20MHz)
• Supports LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL,
and HSTL output modes
• Differential output swing is selectable: 400mV / 650mV /
800mV / 910mV
• Independent output voltages of 3.3V, 2.5V, or 1.8V
▪ LVCMOS additionally supports 1.5V or 1.2V
• The clock phase of each output is individually programmable
in 1ns to 2ns steps with a total range of ±180°
▪ 4 differential / 8 single-ended clock inputs
• Supports frequencies from 1kHz to 1GHz
• Any input can be mapped to any or all of the timing channels
• Redundant inputs frequency independent of each other
• Any input can be designated as external frame/sync pulse of
PPES (pulse per even second), 1PPS (Pulse per Second),
5PPS, 10PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz
associated with a selectable reference clock input
• Per-input programmable phase offset of up to ±1.638s in
50ps steps
▪ Reference monitors qualify/disqualify references depending on
LOS, activity, frequency monitoring, and/or LOS input pins
• Loss of Signal (LOS) input pins (via GPIOs) can be assigned
to any input clock reference
▪ Automatic reference selection state machines select the active
reference for each DPLL based on the reference monitors,
priority tables, revertive / non-revertive, and other
programmable settings
▪ System APLL operates from fundamental-mode crystal: 25MHz
to 54MHz or from a crystal oscillator
▪ System DPLL accepts an XO, TCXO, or OCXO operating at
virtually any frequency from 1MHz to 150MHz
▪ DPLLs can be configured as DCOs to synthesize clocks under
the control of an external algorithm
• DCOs generate with frequency resolution less than
1.11 × 10-16
▪ Supports 1MHz I2
C or 50MHz SPI serial processor ports
▪ Can configure itself automatically after reset via:
• Internal customer definable One-Time Programmable (OTP)
memory with up to 16 different configurations
• Standard external I2
C EEPROM if serial port in I2
C mode
▪ 1149.1 JTAG Boundary Scan
▪ 10 × 10 mm 72-QFN package