FEATURES
• Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization interface signals per ITU-T G.703
• Differential reference inputs (IN3 to IN8) accept clock frequencies
between 1 PPS and 650 MHz
• Single ended inputs (IN9 to IN14) accept reference clock frequencies between 1 PPS and 162.5 MHz
• Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
• Reference monitors qualify/disqualify references depending on
activity, frequency and LOS pins
• Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority
tables, revertive and non-revertive settings and other programmable settings
• Fractional-N input dividers enable the DPLLs to lock to a wide
range of reference clock frequencies including: 10/100/1000 Ethernet, 10G/40G/100G Ethernet, OTN, SONET/SDH, PDH, TDM,
GSM, CPRI and GNSS frequencies
• Any reference input (IN3 to IN14) can be designated as external
sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a
selectable reference clock input
• FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input
and frequency locked to the associated reference clock input
• DPLL1 and DPLL2 can be configured with bandwidths between
0.09 mHz and 567 Hz
• DPLL1 and DPLL2 lock to input references with frequencies
between 1 PPS and 650 MHz
• DPLL3 locks to input references with frequencies between 8 kHz
and 650 MHz
• DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous
Ethernet Equipment Clock (EEC), and G.813 for Synchronous
Equipment Clock (SEC); and Telcordia GR-253-CORE for Stratum
3 and SONET Minimum Clock (SMC)
• DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/
OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks
are directly available on OUT1
• DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE
1588 clocks
• DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output
on OUT9 and OUT10
• APLL1, APLL2 and APLL3 can be connected to DPLL1 or DPLL2
• APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet,
or SONET/SDH frequencies
• APLL3 generates 10G/40/G100G Ethernet, WAN-PHY and LANPHY frequencies
• Any of eight common TCXO/OCXO frequencies can be used for
the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz,
20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
• The I2C slave interface can be used by a host processor to access
the control and status registers
• The I2C master interface can automatically load a device configuration from an external EEPROM after reset; APLL3 must be configured via the I2C slave interface
• DPLL1 or DPLL3 can be connected to an internal composite clock
generator that outputs its 64 kHz synchronization signal on OUT8
• Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
• Differential outputs OUT11 and OUT12 output clocks with frequencies up to 650 MHz
• Single ended outputs OUT1, OUT2 and OUT7 output clocks with
frequencies between 1 PPS and 125 MHz
• Single ended outputs OUT9 and OUT10 output clocks N*8kHz multiples up to 100 MHz
• DPLL1 and DPLL2 support independent programmable delays for
each of IN3 to IN14; the delay for each input is programmable in
steps of 0.61 ns with a range of ~±78 ns
• The input to output phase delay of DPLL1 and DPLL2 is programmable in steps of 0.0745 ps with a total range of ±20 μs
• The clock phase of each of the output dividers for OUT1 (from
APLL1) to OUT7 is individually programmable in steps of ~200 ps
with a total range of +/-180°
• 1149.1 JTAG Boundary Scan
• 144-pin CABGA green package

DESCRIPTION
The 82P33831 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE
1588 / Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths
that control: PTP clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with
Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to- input, input-to-output and output-tooutput phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize 100GBASE-R, 40GBASE-R,
10GBASE-R and 10GBASE-W and lower-rate Ethernet interfaces; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time
Stamp Units (TSUs).
The 82P33831 accepts six differential reference inputs and six single ended reference inputs that can operate at common GNSS, Ethernet,
SONET/SDH and PDH frequencies that range in frequency from 1 Pulse Per Second (PPS) to 650 MHz. The device also provides two Alternate Mark
Inversion (AMI) inputs for Composite Clock (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The references are continually monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to all three DPLLs. The
active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on the reference monitors and LOS inputs.
The 82P33831 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 or DPLL2 can lock to the clock reference and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync
signals can have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 or DPLL2 to phase align its frame sync and multi-frame
sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input.
DPLL1 and DPLL2 support four primary operating modes: Free-Run, Locked, Holdover and DCO. In Free-Run mode the DPLLs synthesize clocks
based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term
output frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data acquired while in Locked mode to generate accurate frequencies when input references are not available. In DCO mode the DPLL control loop is opened and the DCO can be controlled by a PTP clock recovery servo running on an external processor to synthesize PTP clocks.
The 82P33831 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock determines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the
DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked and DCO modes.
When used with a suitable system clock, DPLL1 and DPLL2 meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise tolerance, transient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, ITUT G.8263, ITU-T G.8273.2, Telcordia GR-1244 Stratum 3 (S3), Telcordia GR-253-CORE Stratum 3 (S3) and SONET Minimum Clock (SMC).
DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be
used to lock the DPLL directly to a 1 PPS reference. The 69 mHz and the 92 mHz bandwidths can be used for G.8273.2. The 92 mHz bandwidth can
be used for G.8262/G.813 Option 2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used
for G.8262/G.813 Option 1 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.
DPLL1 and DPLL2 are each connected to Time of Day (ToD) counters or time accumulators; these ToD counters/time accumulators can be used
to track differences between the two time domains and to time-stamp external events by using reference inputs as triggers.
DPLL3 supports three primary operation modes: Free-Run, Locked and Holdover. DPLL3 is a wideband (BW > 25Hz) frequency translator that can
be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048 MHz synchronization interface clock.
In Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per ITU-T G.8275.2, DPLL1 and DPLL2 are both used;
one DPLL is configured as a DCO to synthesize PTP clocks and the other DPLL is configured as an EEC/SEC to generate physical layer clocks.
Combo mode provides physical layer frequency support from the EEC/SEC to the PTP clock.