FEATURES
• Industry standard pinout and timing • All inputs, outputs and clocks are fully TTL compatible Single +5V±10% power supply Low power, 15mW standby: 150mW active, typical . Common I/O capability using "EARLY-WRITE" • Optional PAGE MODE access cycle • Refresh modes: RAS-ONLY CAS-BEFORE-RAS, and HIDDEN 256-cycle refresh distributed across 4ms Specifications guaranteed over full military DRAM temperature range (-55°C to +125°C) .

DESCRIPTION
The AS4C1259 883C is a randomly accessed solid-state memory containing 262,144 bits organized in a xl configu- ration. The 18 address bits are entered 9 bits at a time using RAS to latch the first 9 bits and CAS the latter 9 bits. If the WE pin goes LOW prior to CAS going LOW, the output pin remains open until the next CAS cycle. If WE goes LOW after data reaches the output pin, the output pin is activated and retains the selected cell data as long as CAS remains LOW (regardless of WE or RAS). This late WE pulse results in a READ-MODIFY-WRITEcycle. Data in is latched when WE strobes LOW. By holding RAS LOW, CAS may be toggled to execute several faster READ, WRITE, READ-WRITE or READ. MODIFY-WRITE cycles within the RAS address defined page boundary. Returning RAS HIGH terminates the mem- ory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS HIGH time. Memory cell data is retained in its correct state by maintaining power and executing a RA S (READ, WRITE, RAS-ONLY or HIDDEN REFRESH) cycle so that all 256 combinations of RAS addresses are executed at least every 4ms (regardless of sequence).