Features
• Four differential HSTL compatible outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL, SSTL
• PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to HSTL levels with
resistor bias on nCLK input
• Additive phase jitter, RMS: 0.082ps (typical), 100MHz fOUT
• Additive phase jitter, RMS: 0.190ps (typical), 120MHz fOUT
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.6ns (maximum)
• 3.3V core, 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free packages