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74LVC162373A 데이터시트 (PDF) - Nexperia B.V. All rights reserved

74LVC162373A Datasheet PDF - Nexperia B.V. All rights reserved
부품명 74LVC162373A
다운로드  74LVC162373A 다운로드
파일 크기   246.02 Kbytes
페이지   14 Pages
제조업체  NEXPERIA [Nexperia B.V. All rights reserved]
홈페이지  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
상세설명 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

74LVC162373A Datasheet (PDF)

Go To PDF Page 다운로드 데이터시트
74LVC162373A Datasheet PDF - Nexperia B.V. All rights reserved

부품명 74LVC162373A
다운로드  74LVC162373A Click to download

파일 크기   246.02 Kbytes
페이지   14 Pages
제조업체  NEXPERIA [Nexperia B.V. All rights reserved]
홈페이지  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
상세설명 16-bit D-type transparent latch; 30 Ω series termination resistors; 5 V tolerant inputs/outputs; 3-state

74LVC162373A 데이터시트 (HTML) - Nexperia B.V. All rights reserved


74LVC162373A 제품 세부 정보

1. General description
The 74LVC162373A and 74LVCH162373A are 16-bit D-type transparent latches with 30 Ω
termination resistors and 3-state outputs. The 74LVCH162373A has separate D-type inputs with
bus hold for each latch. Both devices can be used as two 8-bit transparent latches or a single 16-
bit transparent latch. Both devices feature two latch enables (1LE and 2LE) and two output enables
(1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches.
In this condition the latches are transparent, a latch output will change each time its corresponding
D-input changes. When nLE is LOW the latches store the information that was present at the inputs
a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to
assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the
latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
These devices are fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the devices
when they are powered down.
2. Features and benefits
• Overvoltage tolerant inputs to 5.5 V
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Multibyte flow-through standard pinout architecture
• Multiple low inductance supply pins for minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold (74LVCH162373A only)
• IOFF circuitry provides partial Power-down mode operation
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C




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유사한 설명 - 74LVC162373A

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