DESCRIPTION 一 The 167 contains asynchronous decade counter and four
decoding gates that serve to gate the clock through to the output at a sub-
multiple of the clock frequency. The output pulse rate, relative to the clock
frequency, is determined by signals applied to the Select (So 一 Ss) inputs.
Both true and complement outputs are available, along with an enable input
for each. A Count Enable input and a Terminal Count output are provided
for cascading two or more packages. Asynchronous Master Resetand Master
Set inputs prevent counting and clear the counter or set it to maximum
respectively.