1. General description
The 74ABT74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP),
set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that
meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored
in the flip-flop and appear at the Q output. This device is fully specified for partial power down
applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging
backflow current through the device when it is powered down.
2. Features and benefits
• Supply voltage range from 4.5 V to 5.5 V
• BiCMOS high speed and output drive
• Direct interface with TTL levels
• Power-up 3-state
• IOFF circuitry provides partial Power-down mode operation
• Latch-up protection exceeds 500 mA per JESD78B class II level A
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Specified from -40 °C to +85 °C