Features
The i.MX 7Solo family of processors is based on Arm Cortex-A7 MPCore™ Platform, which has the
following features:
• Arm Cortex-A7 Core (with TrustZone® technology)
• The core includes:
— 32 KByte L1 Instruction Cache
— 32 KByte L1 Data Cache
— Private Timer and Watchdog
— NEON MPE (media processing engine) coprocessor
The Arm Cortex-A7 Core complex shares:
• General interrupt controller (GIC) with 128 interrupt support
• Global timer
• Snoop control unit (SCU)
• 512 KB unified I/D L2 cache
• Two master AXI bus interfaces output of L2 cache
• Frequency of the core (including NEON and L1 cache), as per Table 9.
• NEON MPE coprocessor
— SIMD Media Processing Architecture
— NEON register file with 32x64-bit general-purpose registers
— NEON Integer execute pipeline (ALU, Shift, MAC)
— NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
— NEON load/store and permute pipeline
The Arm Cortex-M4 platform:
• Cortex-M4 CPU core
• MPU (memory protection unit)
• FPU (floating-point unit)
• 16 KByte instruction cache
• 16 KByte data cache
• 64 KByte TCM (tightly-coupled memory)
The SoC-level memory system consists of the following additional components:
— Boot ROM, including HAB (96 KB)
— Internal multimedia / shared, fast access RAM (256 KB of total OCRAM)
— Secure/nonsecure RAM (32 KB)
• External memory interfaces: The i.MX 7Solo family of processors supports the latest,
high-volume, cost effective DRAM, NOR, and NAND Flash memory standards.
— Up to 32-bit LP-DDR2-1066, DDR3-1066, DDR3L-1066, and LPDDR3-1066
— 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 62 bits.
— 16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
Each i.MX 7Solo processor enables the following interfaces to external devices (some of them are muxed
and not available simultaneously):
• Displays—Available interfaces.
— One parallel 24-bit display port
— One MIPI DSI port
• Camera sensors:
— One parallel Camera port (up to 24 bit and up to 133 MHz peak)
— One MIPI-CSI port
• Expansion cards:
— Three MMC/SD/SDIO card ports all supporting the following. Moreover, the third port can
support HS400.
– 1-bit or 4-bit transfer mode specifications for SD and SDIO cards, up to 208 MHz
– 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 200 MHz in both
SDR and DDR modes, including HS200 and HS400 DDR modes
• USB:
— One high-speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
— One high-speed USB 2.0 (480 Mbps) host with integrated HSIC USB (high-speed inter-chip
USB) PHY
• Miscellaneous IPs and interfaces:
— Three instances of SAI supporting up to three I2S and AC97 ports
— Seven UARTs, up to 4.0 Mbps:
– Providing RS232 interface
– Supporting 9-bit RS485 Multidrop mode
— Four eCSPI (Enhanced CSPI)
— Four I2C, supporting 400 kbps
— 1-gigabit Ethernet controller (designed to be compatible with IEEE Std 1588), 10/100/1000
Mbps with AVB support
— Four pulse width modulators (PWM)
— System JTAG controller (SJC)
— GPIO with interrupt capabilities
— 8x8 key pad port (KPP)
— One quad SPI
— Four watchdog timers (WDOG)
— One (12 x 12 mm) or two (19 x 19 mm) 2-channel, 12-bit analog-to-digital converters
(ADC)—effective number of bits (ENOB) can vary (typically 9–10 bits) depending on the
system implementation and the condition of the power/ground noise condition
The i.MX 7Solo family of processors integrates advanced power management unit and controllers:
• PMU (power-management unit), multiple LDO supplies, for on-chip resources
• Temperature sensor for monitoring the die temperature
• Software state retention and power gating for Arm and NEON
• Support for various levels of system power modes
• Flexible clock gating control scheme
The i.MX 7Solo family of processors uses dedicated hardware accelerators to meet the targeted
multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance
at low power consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 7Solo family of processors incorporates the following hardware accelerators:
• PXP—PiXel processing pipeline for imagine resize, rotation, overlay and CSC. Off loading key
pixel processing operations are required to support the LCD.
Security functions are implemented by the following hardware:
• Arm TrustZone technology including separation of interrupts and memory mapping
• SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or
blocking the access to the system debug features.
• CAAM—Cryptographic Acceleration and Assurance Module, containing cryptographic and hash
engines, 32 KB secure RAM, and true and pseudo random number generator.
• SNVS—Secure Non-Volatile Storage, including secure real time clock
• CSU—Central Security Unit. Responsible for setting comprehensive security policy of the device.
Configured during boot and by eFuses and determines the security-level operation mode as well as
the TrustZone policy.
• HAB—High Assurance Boot—HABv4 with the new embedded enhancements: SHA-256,
2048-bit RSA key, SRK revocation mechanism, warm boot, CSU, and TrustZone initialization.