Features
• CPU Running up to 800 MHz
– ARM926EJ-S Arm Thumb® processor
– 32-Kbyte data cache, 32-Kbyte instruction cache, Memory Management Unit (MMU)
• Memories
– One 176-Kbyte internal ROM
• 80-Kbyte internal ROM embedding a secure bootloader program supporting boot on NAND Flash,
SD Card, SPI or QSPI Flash; bootloader features selectable by OTP bits
• 96-Kbyte ROM for NAND Flash BCH ECC table
– One 64-Kbyte internal SRAM (SRAM0), single cycle access at system speed
– Internal DDR3L SDRAM running at up to 266 MHz
– External Bus Interface (EBI) supporting:
• 8-bit NAND Flash with up to 24-bit programmable multi-bit error correcting code
– One 10-Kbyte OTP memory for secure key storage with Emulation mode (OTP bits are emulated by a
4-Kbyte SRAM (SRAM1))
• System Running up to 266 MHz
– Power-on reset cells, reset controller, shutdown controller, periodic interval timer, watchdog timer
running on internal slow RC oscillator (32 kHz typical) and real-time clock running on slow crystal
oscillator (32.768 kHz)
– Two internal trimmed RC oscillators with typical values: 32 kHz (slow) and 12 MHz (fast)
– Two crystal oscillators: 32.768 kHz (slow) and 20 to 50 MHz (fast)
– One PLL for the system and one PLL optimized for USB high-speed operation (480 MHz)
• One PLL for audio operations, with dedicated output clock
• One PLL in LVDS I/F (LVDS usage only)
• One PLL in MIPI DPHY (MIPI DSI usage only)
– One dual-port 16-channel DMA controller
– Advanced interrupt controller and debug unit
– JTAG port with disable bit in OTP memory
– Two programmable clock output signals
• Low-Power Modes
– Backup mode with RTC, eight 32-bit general purpose backup registers, and shutdown controller to
control the external power supply
– Clock generator and power management controller
– Software-programmable ultra-low power modes: very slow clock operating mode (ULP0) and no-clock
operating mode (ULP1) with fast wake-up capabilities
– Software programmable power optimization capabilities
• Peripherals
– LCD controller with overlay, alpha blending, rotation, scaling and color conversion; up to 720p resolution
• RGB, LVDS, MIPI-DSI interfaces
– 2D graphics controller supporting fill BLT, copy BLT, transparent BLT, blend/alpha BLT, ROP4 BLT (raster
operations) and command ring buffer
– Image sensor controller with ITU-R BT; 601/656/1120 video interface support up to 5 Mpixels; support of
raw Bayer 12, YCbCr, monochrome and JPEG compressed sensors up to 12 bits
• MIPI CSI2 I/F support
• 12-bit parallel I/F support
– One high-speed USB device, three high-speed USB hosts with dedicated on-chip transceivers
– One 10/100/1000 Mbps Ethernet Mac controller with IEEE-1588 and TSN support, RGMII and RMII
support
– Two 4-bit secure digital multimedia card controllers
– Two CAN FD controllers with timestamping
– One Quad/Octal SPI controller
– Two 3-channel 32-bit timers/counters
– Two high-resolution (64-bit) periodic interval timers
– One synchronous serial controller
– One inter-IC sound multi-channel controller with TDM support
– One audio class D controller with single-ended or bridge-tied load connection to power stage
– One 4-channel 16-bit PWM controller
– Thirteen FLEXCOMs (USART, SPI and TWI/I2C)
– One 8-channel, 12-bit, analog-to-digital converter with 4/5 wires resistive touchscreen support
• Hardware Cryptography
– SHA (SHA1, SHA224, SHA256, SHA384, SHA512) and HMAC compliant with FIPS PUB 180
– AES: 256-, 192-, 128-bit key algorithms compliant with FIPS PUB 197
– AES/SHA tight coupling for IPsec hardware acceleration
– TDES: 2-key or 3-key algorithms compliant with FIPS PUB 46
– True random number generator compliant with NIST Special Publication 800-22 Test Suite and FIPS PUBs
140-2 and 140-3
– Key bus providing private key transfers between AES, TDES, TRNG, OTPC
– Physical Unclonable Function (PUF) including NIST SP 800-90B (DRNG) and embedding four Kbytes of
SRAM (PUFSRAM)
• I/O Ports
– Four 32-bit parallel input/output controllers
– Up to 106 programmable I/O lines multiplexed with up to four peripheral I/Os
– Input change interrupt capability on each I/O line, optional Schmitt trigger input
– Individually programmable open-drain, pull-up and pull-down resistors, synchronous output
– General-purpose analog and digital inputs tolerant to positive and negative current injection
• Package
– 16x16 mm2, 0.8-mm pitch, 243-ball BGA optimized for standard class PCB layout (down to four layers)
• Design for low ElectroMagnetic Interference (EMI)
– Slewrate-controlled I/Os
– DDR PHY with impedance-calibrated drivers
– Spread spectrum PLLs
– BGA power/ground ball assignment to provide optimum decoupling capacitors placement
• Operating Conditions
– Junction temperature (TJ) range: -40°C to +125°C
– Ambient temperature (TA) range: -40°C to +85°C