1FEATURES
2• Internal Sample-and-Hold Circuit and Precision
Reference
• Low Power Consumption
• Clock Duty Cycle Stabilizer
• Single +3.0V or +3.3V Supply Operation
• Power-Down Mode
• Offset Binary or 2's Complement Output Data
Format
• 60-Pin WQFN Package, (9x9x0.8mm, 0.5mm
Pin-Pitch)

KEY SPECIFICATIONS
• Resolution: 12 Bits
• Conversion Rate: 105 MSPS
• SNR (fIN = 170 MHz): 69 dBFS (Typ)
• SFDR (fIN = 170 MHz): 83 dBFS (Typ) pin•
Full Power Bandwidth: 1 GHz (Typ)
• Power Consumption
– 690 mW (Typ), V A = 3.0V
– 800 mW (Typ), VA = 3.3V

APPLICATIONS
• High IF Sampling Receivers
• Wireless Base Station Receivers
• Test and Measurement Equipment
• Communications Instrumentation
• Portable Instrumentation

DESCRIPTION
The ADC12DC105 is a high-performance CMOS
analog-to-digital converter capable of converting two
analog input signals into 12-bit digital words at rates
up to 105 Mega Samples Per Second (MSPS). These
converters use a differential, pipelined architecture
with digital error correction and an on-chip sampleand-
hold circuit to minimize power consumption and
the external component count, while providing
excellent dynamic performance. A unique sample-
and-hold stage yields a full-power bandwidth of 1
GHz. The ADC12DC080/105 may be operated from a
single +3.0V or +3.3V power supply. A power-down
feature reduces the power consumption to very low
levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full
scale differential input swing. A stable 1.2V internal
voltage reference is provided, or the ADC12DC105
can be operated with an external 1.2V reference.
Output data format (offset binary versus 2's
complement) and duty cycle stabilizer are pin•
selectable. The duty cycle stabilizer maintains
performance over a wide range of clock duty cycles.
The ADC12DC105 is available in a 60-lead WQFN
package and operates over the industrial temperature
range of −40°C to +85°C.