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ISO721M-EP 데이터시트 (PDF) - Texas Instruments

ISO721M-EP Datasheet PDF - Texas Instruments
부품명 ISO721M-EP
다운로드  ISO721M-EP 다운로드
파일 크기   713.48 Kbytes
페이지   27 Pages
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments
상세설명 3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS

ISO721M-EP Datasheet (PDF)

Go To PDF Page 다운로드 데이터시트
ISO721M-EP Datasheet PDF - Texas Instruments

부품명 ISO721M-EP
다운로드  ISO721M-EP Click to download

파일 크기   713.48 Kbytes
페이지   27 Pages
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments
상세설명 3.3-V/5-V HIGH-SPEED DIGITAL ISOLATORS

ISO721M-EP 데이터시트 (HTML) - Texas Instruments


ISO721M-EP 제품 세부 정보

1FEATURES
23· Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
· Extended Temperature Performance of
–55°C to 125°C
· Enhanced Diminishing Manufacturing Sources
(DMS) Support
· Enhanced Product-Change Notification
· Qualification Pedigree (1)
· 4000-V(peak) Isolation
– UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1
– 50-kV/ms Transient Immunity Typical
· Signaling Rate 0 Mbps to 150 Mbps
– Low Propagation Delay
– Low Pulse Skew (Pulse-Width Distortion)
· Low-Power Sleep Mode
· High Electromagnetic Immunity
· Low Input Current Requirement
· Failsafe Output
· Drop-In Replacement for Most Opto and
Magnetic Isolators

APPLICATIONS
· Industrial Fieldbus
– Modbus
– Profibus
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
· Computer Peripheral Interface
· Servo Control Interface
· Data Acquisition

DESCRIPTION/ORDER INFORMATION
The ISO721, ISO721M, ISO722, and ISO722M are digital isolators with a logic input and output buffer separated
by a silicon oxide (SiO2) insulation barrier. This barrier provides galvanic isolation of up to 4000 V. Used in
conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuits
from entering the local ground, and interfering with or damaging sensitive circuitry.
A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation
barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or
resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure
the proper dc level of the output. If this dc-refresh pulse is not received for more than 4 ms, the input is assumed
to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state.




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