Functionally Equivalent to AMD’s AM29823
and AM29824
Provide Extra Data Width Necessary for
Wider Address/Data Paths or Buses With
Parity
Outputs Have Undershoot-Protection
Circuitry
Power-Up High-Impedance State
Buffered Control Inputs to Reduce
dc Loading Effects
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs

description
These 9-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. These devices
are particularly suitable for implementing wider
buffer registers, I/O ports, bidirectional bus
drivers, parity bus interfacing, and working
registers.
With the clock-enable (CLKEN) input low, the nine
D-type edge-triggered flip-flops enter data on the
low-to-high transitions of the clock (CLK) input.
Taking CLKEN high disables the clock buffer,
latching the outputs. The SN54AS823A and
SN74AS823A have noninverting data (D) inputs
and the SN74AS824A has inverting (D) inputs.
Taking the clear (CLR) input low causes the nine
Q outputs to go low independently of the clock.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic level) or the highimpedance
state. In the high-impedance state, the
outputs neither load nor drive the bus lines
significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operation of the
flip-flops. Old data can be retained or new data
can be entered while the outputs are in the
high-impedance state.
The SN54AS823A is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74AS823A and SN74AS824A
are characterized for operation from 0°C to 70°C.