Members of the Texas Instruments
WidebusE Family
State-of-the-Art EPIC-IIBE BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description
The ’ABT16623 are 16-bit transceivers designed
for asynchronous communication between data
buses. The control-function implementation
allows for maximum flexibility in timing. The
’ABT16623 provide true data at the outputs.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
levels at the output-enable (OEAB and OEBA)
inputs. The output-enable inputs can be used to
disable the device so that the buses are effectively
isolated. The dual-enable configuration gives the
transceivers the capability of storing data by
simultaneously enabling OEAB and OEBA. Each
output reinforces its input in this configuration.
When both OEAB and OEBA are enabled and all
other data sources to the two sets of bus lines are
at high impedance, both sets of bus lines (32 total)
remain at their last states.