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SN74LVC1G374 데이터시트 (PDF) - Texas Instruments

SN74LVC1G374 Datasheet PDF - Texas Instruments
부품명 SN74LVC1G374
다운로드  SN74LVC1G374 다운로드
파일 크기   740.79 Kbytes
페이지   22 Pages
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments
상세설명 Single D-Type Flip-Flop With 3-State Output

SN74LVC1G374 Datasheet (PDF)

Go To PDF Page 다운로드 데이터시트
SN74LVC1G374 Datasheet PDF - Texas Instruments

부품명 SN74LVC1G374
다운로드  SN74LVC1G374 Click to download

파일 크기   740.79 Kbytes
페이지   22 Pages
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments
상세설명 Single D-Type Flip-Flop With 3-State Output

SN74LVC1G374 데이터시트 (HTML) - Texas Instruments


SN74LVC1G374 제품 세부 정보

1FEATURES
2• Available in the Texas Instruments NanoStar™
and NanoFree™ Packages
• Supports 5-V V CC Operation
• Inputs Accept Voltages to 5.5 V
• Provides Down Translation to VCC
• Max tpd of 4 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Live Insertion, Partial-Power-
Down Mode, and Back Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

DESCRIPTION
This single D-type latch is designed for 1.65-V to 5.5-
V VCC operation.
The SN74LVC1G374 features a 3-state output
designed specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer registers,
input/output (I/O) ports, bidirectional bus drivers, and
working registers.
NanoStar™ and NanoFree™ package technology is
a major breakthrough in IC packaging concepts,
using the die as the package.
On the positive transition of the clock (CLK) input, the
Q output is set to the logic level set up at the data (D)
input.
A buffered output-enable (OE) input can be used to
place the output in either a normal logic state (high or
low logic levels) or the high-impedance state. In the
high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance
state and increased drive provide the capability to
drive bus lines without interface or pullup
components.
OE does not affect the internal operations of the flip-
flop. Old data can be retained or new data can be
entered while the outputs are in the high-impedance
state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.




유사한 부품 번호 - SN74LVC1G374

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