1 Features
• Buffered inputs
• Asynchronous parallel load
• Complementary outputs
• Fanout (over temperature range)
– Standard outputs: 10 LSTTL Loads
– Bus driver outputs: 15 LSTTL Loads
• Wide operating temperature range: -55℃ to 125℃
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL
Logic ICs
• HC Types
– 2 V to 6 V Operation
– High Noise Immunity: NIL = 30%, NIH = 30% of
VCC at VCC = 5V
• HCT Types
– 4.5 V to 5.5 V Operation
– Direct LSTTL Input Logic Compatibility,
VIL = 0.8 V (Max), VIH = 2 V (Min)
– CMOS Input Compatibility, II ≤ 1 μA at VOL, VOH

2 Description
The ’HC165 and ’HCT165 are 8-bit parallel or serialin
shift registers with complementary serial outputs
(QH and Q H) available from the last stage. When
the parallel load (SH/LD) input is LOW, parallel data
from the A to H inputs are loaded into the register
asynchronously. When the SH/LD is HIGH, data
enters the register serially at the SER input and shifts
one place to the right (A→B→C, etc.) with each
positive-going clock transition. This feature allows
parallel-to-serial converter expansion by connecting
the QH output to the SER input of the succeeding
device.