1 Features
• 9 to 100-V, Triple half-bridge gate driver
– Extended TA operation -55 °C to 125 °C
– Optional triple low-side current shunt amplifiers
• Smart gate drive architecture
– Adjustable slew rate control for EMI
performance
– VGS handshake and minimum dead-time
insertion to prevent shoot-through
– 50-mA to 1-A peak source current
– 100-mA to 2-A peak sink current
– dV/dt mitigation through strong pulldown
• Integrated gate driver power supplies
– High-side doubler charge pump For 100%
PWM duty cycle control
– Low-side linear regulator
• Integrated triple current shunt amplifiers
– Adjustable gain (5, 10, 20, 40 V/V)
– Bidirectional or unidirectional support
• 6x, 3x, 1x, and independent PWM modes
– Supports 120° sensored operation
• SPI or hardware interface available
• Low-power sleep mode (20 μA at VVM = 48-V)
• Integrated protection features
– VM undervoltage lockout (UVLO)
– Gate drive supply undervoltage (GDUV)
– MOSFET VDS overcurrent protection (OCP)
– MOSFET shoot-through prevention
– Gate driver fault (GDF)
– Thermal warning and shutdown (OTW/OTSD)
– Fault condition indicator (nFAULT)

2 Applications
• 3-phase brushless-DC (BLDC) motor modules
• Fans, blowers, and pumps

3 Description
The DRV8353M family of devices are highlyintegrated
gate drivers for three-phase brushless DC
(BLDC) motor applications. These applications
include field-oriented control (FOC), sinusoidal current
control, and trapezoidal current control of BLDC
motors. The device variants provide optional
integrated current shunt amplifiers to support different
motor control schemes and a buck regulator to power
the gate driver or external controller.
The DRV8353M uses smart gate drive (SGD)
architecture to decrease the number of external
components that are typically necessary for MOSFET
slew rate control and protection circuits. The SGD
architecture also optimizes dead time to prevent
shoot-through conditions, provides flexibility in
decreasing electromagnetic interference (EMI) by
MOSFET slew rate control, and protects against gate
short circuit conditions through VGS monitors. A strong
gate pulldown circuit helps prevent unwanted dV/dt
parasitic gate turn on events
Various PWM control modes (6x, 3x, 1x, and
independent) are supported for simple interfacing to
the external controller. These modes can decrease
the number of outputs required of the controller for the
motor driver PWM control signals. This family of
devices also includes 1x PWM mode for simple
sensored trapezoidal control of a BLDC motor by
using an internal block commutation table.