1 Features
• High-performance LVDS clock buffer family with 2
inputs and 4 (2:4) or 8 (2:8) outputs.
• Output frequency up to 2 GHz.
• Supply voltage: 1.71 V to 3.465 V
• Low additive jitter: < maximum 60 fs RMS in 12-
kHz to 20-MHz at 156.25 MHz
– Very low phase noise floor: –164 dBc/Hz
(typical)
• Very low propagation delay: < 575 ps maximum
• Output skew: 20 ps maximum
• Universal inputs accept LVDS, LVPECL, LVCMOS,
LP-HCSL, HCSL and CML inputs
• LVDS reference voltage, VAC_REF, available for
capacitive-coupled inputs
• Industrial temperature range: –40°C to 105°C
• Packages available:
– LMK1D1204: 3-mm × 3-mm, 16-pin VQFN
(RGT)
– LMK1D1208: 5-mm × 5-mm, 28-pin VQFN
(RHD)

2 Applications
• Telecommunications and networking
• Medical imaging
• Test and measurement
• Wireless infrastructure
• Pro audio, video and signage

3 Description
The LMK1D120x clock buffer distributes one of two
selectable clock inputs (IN0 and IN1) to 4 or 8 pairs
of differential LVDS clock outputs (OUT0 through
OUT7) with minimum skew for clock distribution. The
LMK1D12x family can accept two clock sources into
an input multiplexer. The inputs can either be LVDS,
LVPECL, LP-HCSL, HCSL, CML or LVCMOS.
The LMK1D12x is specifically designed for driving 50-
Ω transmission lines. In case of driving the inputs in
single-ended mode, the appropriate bias voltage as
shown in Figure 9-6 must be applied to the unused
negative input pin.
The IN_SEL pin selects the input which is routed
to the outputs. If this pin is left open, it disables
the outputs (logic low). The part supports a fail-safe
function. The device further incorporates an input
hysteresis which prevents random oscillation of the
outputs in the absence of an input signal.
The device operates in 1.8-V or 2.5-V or 3.3-V
supply environment and is characterized from –40°C
to 105°C (ambient temperature). The LMK1D12x
package variant is shown in the table below: