FEATURES
Receive path includes
Simultaneous sampling 32 MSPS I/Q SHA
64 MSPS 14-bit muxed ADC with 77 dBFS SNR
Bypassable 2nd order CIC and 64-tap FIR decimation filters
Transmit path includes
Dual 12-bit, 32 MSPS TxDAC
Bypassable 64-tap FIR and 3rd order CIC decimation filters
Auxiliary converters includes
Dual 10-bit voltage output DACs
Three 10-bit SAR muxed ADCs—10 analog inputs
Programmable full-scale input/output levels
Flexible DSP and digital interface includes
Bidirectional 16-bit Tx/Rx data port
Supports interleaved Rx and Tx I/Q data as well as noninterleaved Tx data
9 programmable GPIOs
3- or 4-wire SPI interface
SPI-configurable registers allow programmability of IC and access to auxiliary converters and GPIOs
Internal clock doubler and timing generation circuitry
80-lead LQFP package