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XM33C321ASPZR 데이터시트 (PDF) - Texas Instruments

XM33C321ASPZR Datasheet PDF - Texas Instruments
부품명 XM33C321ASPZR
다운로드  XM33C321ASPZR 다운로드
파일 크기   4385.19 Kbytes
페이지   122 Pages
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments
상세설명 MSPM33C321x Mixed-Signal Microcontrollers

XM33C321ASPZR Datasheet (PDF)

Go To PDF Page 다운로드 데이터시트
XM33C321ASPZR Datasheet PDF - Texas Instruments

부품명 XM33C321ASPZR
다운로드  XM33C321ASPZR Click to download

파일 크기   4385.19 Kbytes
페이지   122 Pages
제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments
상세설명 MSPM33C321x Mixed-Signal Microcontrollers

XM33C321ASPZR 데이터시트 (HTML) - Texas Instruments


XM33C321ASPZR 제품 세부 정보

1 Features
• Core
– 160MHz Arm® 32-bit Cortex®-M33 CPU with TrustZone®, FPU, and DSP extensions
– 4kB instruction cache for 0 wait-state execution
• Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.71V to 3.6V
• Memories
– Up to 1MB of flash memory with error correction code (ECC)
• Dual-bank with address swap
– 256kB of SRAM with ECC
– EEPROM operations using 32kB highendurance data flash
• Security
– Immutable Root of Trust (RoT) in ROM, supports secure firmware installation, boot and key provisioning
– Global Security Controller (GSC) with dynamic access controls for flash, SRAM, and peripherals
– AES256 hardware accelerator with GCM
– SHA256 hardware accelerator with HMAC
– Public Key Accelerator (PKA) supports ECC and RSA
– True random number generator (TRNG)
• High-performance analog peripherals
– Two high-speed simultaneous sampling 9.4Msps 12-bit analog-to-digital converters (ADCs) with up to 36 external channels
– Two high-speed/low-power comparators (COMP)
– Two externally available 8-bit DACs
– Configurable 1.4V or 2.5V internal shared voltage reference (VREF)
– Integrated temperature & supply monitor
• Optimized low-power modes
– RUN: 211μA/MHz (CoreMark)
– SLEEP: 3.8mA at 32MHz
– STOP: 143μA at 4MHz
– STANDBY: 8μA with CPU execution resume and 64kB SRAM retention
– SHUTDOWN: <100nA with IO wake-up capability




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